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2.10.15 JP14, JP15, JP16, Oscillator Selection

Jumpers JP14, JP15, and JP16 are used together to select different clock modes and

speeds for the C54XX DSP. The EVM320C54XX is equipped with a 10 megahertz

oscillator.

The C54XX PLL can be configured in one of the two provided clock modes:

- The input clock (CLKIN) is divided by 2 or 4; this is called DIV mode

- The input clock (VLKIN) is multiplied by one of 31 possible ratios which

range from 0.25 to 15. These ratios are achieved with the Analog Voltage

controlled Oscillator (VCO).; this mode is called PLL mode.

When the PLL clock mode is not used, VCO and all the analog parts are disabled in

order to minimize the power dissipation

The PLL clock mode can be determined by setting 3 external clock mode pins during

reset or by software. In software, a 16 bit register (CLKMD) controls the behavior of the

PLL and sets the mode.

At start-up the clock mode is selected with the values on input pins CLKMD1, CLKMD2,

and CLKMD3. These these pins are tied to jumpers JP14, JP15, and JP16 respectively.

The configuration is shown in the table below.

Table 29: JP14, JP15, JP16, Clock Mode Table

JP14,

CLKMD1

JP15,

CLKMD2

JP16,

CLKMD3

Clock Mode/CLKMD Value Upon Reset

2-3 1-2 2-3 1/2 with external source, CLKMD = 0000h

1-2 2-3 2-3 1/2 with external source, CLKMD = 6000h

1-2 1-2 2-3 1/2 with external source, CLKMD = 4000h

2-3 2-3 2-3 1/2 with external source, CLKMD = 2000h

2-3 1-2 1-2 1/2 with external source, CLKMD = 1000h

2-3 2-3 1-2 Stop mode, CLKMD = na

1-2 1-2 1-2 PLL * 1 with external source, CLKMD = 7000h

1-2 2-3 1-2 1/2 with external source, CLKMD = 7000h

Akura AV26720-HD2 Spezifikationen Seite 43